As contemporary memories have progressed towards ever smaller process scales and lower operating voltages, it is known that it may be necessary to take steps to ensure that read stability is maintained. This relates to the fact that the configuration of a contemporary memory may be at a level where the access disturbance margin (ADM) or static noise margin (SNM) may be such that the action of reading a data bit held by a bit cell of the memory may cause the value of that data bit to change. Such lowered stability can for example result from process variation or low operating voltages.
One known technique for addressing this problem is to lower the voltage applied to the relevant word line for at least part of the read process. By applying a lower voltage to the bit cell access ports (pass gates), in particular during the early portion of the read process, the internal nodes are less disturbed and the bit cell is more stable. Various techniques are known for achieving this lowered voltage on the word line, such as charge injection/extraction solutions, which seek to vary the word line voltage by selectively connecting a capacitive element to it, yet these known techniques are susceptible to process and temperature variation. Moreover, the timing of the application of the “read assist” wordline voltage lowering can be critical.
It would be desirable to provide a technique which enabled such read assist wordline voltage lowering to be implemented, which is less sensitive to temperature and process variations, and is more flexible with regards to timing.